// die Radio 1110 Datei

#ifndef MYCC1110RADIO
#define MYCC1110RADIO

void initcc1110(void);

UINT8 readcc1110Packet(UINT8* buf);
UINT8 sendcc1110Packet(UINT8* buf, UINT8 len, UINT8 rxon);
volatile UINT16 currtime16(void);
void setRxTIO(UINT32 aTio);

#if defined __SDCC__
#define BITVAR __bit
#define SFR(name,addr)   __sfr __at (addr) name;
#define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) __sfr __at (addr) name;
#define SBIT(name,addr)  __bit __at (addr) name;
#define VECT(num,addr)   num
#define XREG(addr) ((__xdata unsigned char volatile *) 0)[addr]
//#error "sdcc detected"
#define CODEVAR(type, name, addr) __code __at (addr) type name
#else
#error "Unrecognized compiler."
#endif

#define SYNC1 XREG( 0xDF00 )   // Sync Word, High Byte............................................  
#define SYNC0 XREG( 0xDF01 )   // Sync Word, Low Byte ............................................ 
#define PKTLEN XREG( 0xDF02 )   // Packet Length.......................................................    
#define PKTCTRL1 XREG( 0xDF03 )   // Packet Automation Control .............................  
#define PKTCTRL0 XREG( 0xDF04 )   // Packet Automation Control .............................  
#define ADDR XREG( 0xDF05 )   // Device Address ........................................................   
#define CHANNR XREG( 0xDF06 )   // Channel Number.................................................    
#define FSCTRL1 XREG( 0xDF07 )   // Frequency Synthesizer Control...........................   
#define FSCTRL0 XREG( 0xDF08 )   // Frequency Synthesizer Control...........................   
#define FREQ2 XREG( 0xDF09 )   // Frequency Control Word, High Byte ......................
#define FREQ1 XREG( 0xDF0A )   // Frequency Control Word, Middle Byte........................................................ 213
#define FREQ0 XREG( 0xDF0B )   // Frequency Control Word, Low Byte ............................................................
#define MDMCFG4 XREG( 0xDF0C )   // Modem configuration............................................................................ 214   
#define MDMCFG3 XREG( 0xDF0D )   // Modem Configuration........................................................................... 214   
#define MDMCFG2 XREG( 0xDF0E )   // Modem Configuration ........................................................................... 215  
#define MDMCFG1 XREG( 0xDF0F )   // Modem Configuration ........................................................................... 216  
#define MDMCFG0 XREG( 0xDF10 )   // Modem Configuration ........................................................................... 216  
#define DEVIATN XREG( 0xDF11 )   // Modem Deviation Setting........................................................................ 217  
#define MCSM2 XREG( 0xDF12 )   // Main Radio Control State Machine Configuration......................................
#define MCSM1 XREG( 0xDF13 )   // Main Radio Control State Machine Configuration......................................
#define MCSM0 XREG( 0xDF14 )   // Main Radio Control State Machine Configuration......................................
#define FOCCFG XREG( 0xDF15 )   // Frequency Offset Compensation Configuration ........................................ 219
#define BSCFG XREG( 0xDF16 )   // Bit Synchronization Configuration ............................................................... 220 
#define AGCCTRL2 XREG( 0xDF17 )   // AGC Control......................................................................................... 221   
#define AGCCTRL1 XREG( 0xDF18 )   // AGC Control......................................................................................... 222   
#define AGCCTRL0 XREG( 0xDF19 )   // AGC Control......................................................................................... 223   
#define FREND1 XREG( 0xDF1A )   // Front End RX Configuration ..................................................................... 223
#define FREND0 XREG( 0xDF1B )   // Front End TX Configuration ..................................................................... 224
#define FSCAL3 XREG( 0xDF1C )   // Frequency Synthesizer Calibration............................................................. 224  
#define FSCAL2 XREG( 0xDF1D )   // Frequency Synthesizer Calibration ............................................................ 224 
#define FSCAL1 XREG( 0xDF1E )   // Frequency Synthesizer Calibration............................................................. 225  
#define FSCAL0 XREG( 0xDF1F )   // Frequency Synthesizer Calibration ............................................................. 225 
#define TEST2 XREG( 0xDF23 )   // Various Test Settings ..................................................................................... 225 
#define TEST1 XREG( 0xDF24 )   // Various Test Settings ..................................................................................... 225 
#define TEST0 XREG( 0xDF25 )   // Various Test Settings ..................................................................................... 225 
#define PA_TABLE7 XREG( 0xDF27 )   // PA Power Setting 7 ............................................................................. 225
#define PA_TABLE6 XREG( 0xDF28 )   // PA Power Setting 6 ............................................................................. 225
#define PA_TABLE5 XREG( 0xDF29 )   // PA Power Setting 5 ............................................................................. 226
#define PA_TABLE4 XREG( 0xDF2A )   // PA Power Setting 4............................................................................. 226 
#define PA_TABLE3 XREG( 0xDF2B )   // PA Power Setting 3............................................................................. 226 
#define PA_TABLE2 XREG( 0xDF2C )   // PA Power Setting 2............................................................................. 226 
#define PA_TABLE1 XREG( 0xDF2D )   // PA Power Setting 1............................................................................. 226 
#define PA_TABLE0 XREG( 0xDF2E )   // PA Power Setting 0 ............................................................................. 226
#define PARTNUM XREG( 0xDF36 )   // Chip ID[15:8]......................................................................................... 226   
#define VERSION XREG( 0xDF37 )   // Chip ID[7:0] ............................................................................................. 226  
#define FREQEST XREG( 0xDF38 )   // Frequency Offset Estimate from Demodulator ........................................
#define LQI XREG( 0xDF39 )   // Demodulator Estimate for Link Quality .............................................................
#define RSSI XREG( 0xDF3A )   // Received Signal Strength Indication ................................................................ 227
#define MARCSTATE XREG( 0xDF3B )   // Main Radio Control State Machine State
#define PKTSTATUS XREG( 0xDF3C )   // Packet Status ...................................................................................... 228  
#define VCO_VC_DAC XREG( 0xDF3D )   // Current Setting from PLL Calibration Module


/* register RFST - command strobes */
#define SFSTXON       0x00
#define SCAL          0x01
#define SRX           0x02
#define STX           0x03
#define SIDLE         0x04

/* register MARCSTATE - state values */
#define RXTX_SWITCH   0x15
#define RX            0x0D
#define IDLE          0x01



#endif
